Principal Investigator

Prof. Yoshio Nishi

Research Staff

Post Doctoral Researchers

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Yoshio Nishi

Prof. Yoshio Nishi Professor, Electrical Engineering (research)
Professor, Materials Science and Engineering (courtesy)

Research Areas

Yoshio Nishi is a professor in the Department of Electrical Engineering (research) and also in the Department of Material Science and Engineering at the Stanford University since May 2002. He also serves as the director of the Stanford Nanofabrication Facility of National Nanotechnology Infrastructure Network of the United States and director of research of the Center for Integrated Systems. He received a BS degree in materials science and a PhD in electronics engineering from Waseda University and the University of Tokyo, respectively.
He researched on semiconductor device physics and silicon interfaces in the Toshiba R&D, which resulted in the discovery of ESR PB Center at SiO2–Si interface, the first 256-bit MNOS nonvolatile RAM, SOS 16-bit microprocessor, and the world’s first 1-MB CMOS DRAM. In 1986 he joined Hewlett-Packard as the director of the Silicon Process Lab, and then established the ULSI Research Lab.
Dr Nishi joined the TI, Inc. in 1995 as the senior vice president and the director of R&D for the semiconductor group, implemented a new R&D model for silicon technology development, and established the Kilby Center.
Since May 2002, he became a faculty member at the Stanford University, and his research interest covers nanoelectronic devices and materials including a metal gate/high-k MOS, a device layer transfer for 3D integration, nanowire devices, and resistance change nonvolatile memory materials and devices. He has published more than 200 papers including conference proceedings, and he coauthored/edited nine books. He holds more than 70 patents in the United States and Japan.
During the period of 1995–2002, he served as a board member of the SRC and the International Sematech, the NNI panel, the MARCO governing council, and other boards. Currently, he serves as an affiliated member of the Science Council of Japan.
Dr Nishi is a fellow of the IEEE, a member of the Japan Society of Applied Physics and the Electrochemical Society. His recent awards include the 1995 IEEE Jack Morton Award and the 2002 IEEE Robert Noyce Medal.

Contact

Office: Paul G. Allen 103, 420 Via Palou
Stanford University
Stanford CA 94305-4070
Phone: (650) 723-9508
Fax: (650) 725-0991
Email: nishiy

Education

Specific Research Interests

Special Projects

Other Information

Selected Publications

  1. M. E. Grubbs, M. Deal, Y. Nishi and B. Clemens, “The Effect of Oxygen on the Work Function of Tungsten Gate Electrodes in MOS Devices” IEEE Electron Devices Letters, Vol. 30, pp. 925-927, 2010
  2. Z. Liu, M. Kobayashi, B. C. Paul, Z. Bao, and Y. Nishi, “Fermi-Level Depinning at Metal-Organic Semiconductor Interface for Low-Resistance Ohmic Contacts”, IEEE International Electron Devices Meeting, December, 2009, Baltimore, MD
  3. X. Zhang, J. Li, M. Grubbs, M. Deal, B. Magyari-Kope, B. Clemens, Y. Nishi, “Physical Model of the Impact of Metal Grain Work Function Variability on Emerging Dual Metal Gate MOSFETs and its Implication for SRAM Reliability”, IEEE International Electron Devices Meeting, December, 2009, Baltimore, MD.
  4. Y.Nishi, “Integration Challenges and Opportunities of Nanoelectronic Devices”, Electrochemical Society meeting, October, 2009, Vienna Autria,
  5. L. Geng, B. Magyari-Kope, Z. Zhang, Y. Nishi, “Fermi level unpinning and Schottky barrier modification by Ti, Sc and V incorporation at NiSi2/Si interface”,Chinese Physics Letters 26, 037306, 2009
  6. S-L Cheng, J. Lu, G. Shambat, H. Y. Yu, K. Saraswat, J. Vuckovic and Y. Nishi.,” Room Temperature 1.6um Electroluminescence from Ge Light Emitting Diode on Si Substrate” Optics Express, vol. 17, 10024 (2009)
  7. M. Kobayashi, A. Kinoshita, K. Saraswat, H-S P Wong and Y. Nishi, “Fermi Level Depinning in Metal/Ge Schottky Junction for Metal Source/Drain Ge Metal-Oxide-Semiconductor Field Effect Transistor Applications”, J. Appl. Phys. 105, 023702, January, 2009
  8. Y. Nishi and J. Jameson, “Recent Progress in Resistance Change Memory” 2008 Device Research Conference, June, 2008, U.C. Santa Barbara, CA
  9. Y. Nishi, “Challenge of Nanoelectronic Materials and Devices toward New Nonvolatile Memories” 9th International Conference on Solid-State and Integrated-Circuit Technology, October, 2008, Beijing, China
  10. P. T. Chen, B. B. Triplett, P.C. McIntyre, Y. Nishi, et al., " Analysis of Electrically Biased Paramagnetic Defect Centers in HfO2 and HfxSi1-xO2/(100)Si Interfaces", Journal of Applied Physics (JAP), 104, 014106 (2008)
  11. M. Kobayashi, P.T. Chen, Y.Sun, N. Goel, P. Majhi, M. Garner, W.Tsai, P. Pianetta, Y. Nishi, “Synchrotron Radiation Photoemission Spectroscopic Study of Band Offsets and Interface Self-Cleaned by Atomic Layer Deposited HfO2 on In0.53Ga0.47As and In0.52Al0.48As” Appl. Phys. Letters vol 93, 182103, 2008
  12. P. T. Chen, Y. Sun, E. Kim, P.C. McIntyre, P. Pianetta, Y. Nishi," HfO2 Gate Dielectric on (NH4)2S Passivated (100) GaAs Grown by Atomic Layer Deposition", Journal of Applied Physics (JAP), 103 , 034106 (2008)
  13. N. Goel, P. Majhi, W. Tsai, M. Warusawithana, D.G. Schlom, M.B. Santos, J.S. Harris, and Y. Nishi, "High-Indium-Content InGaAs Metal-Oxide-Semiconductor Capacitor with Amorphous LaAlO3 Gate Dielectric accepted for Applied Physics Letters (2007)
  14. B. C. Paul, R. Tu, S. Fujita, M. Okajima, T. Lee, and Y. Nishi, "A Circuit Compatible Analytical Device Model for Nanowire FET," IEEE Trans. Electron Devices, Vol. 54, No. 7, pp. 1637-1644, July 2007
  15. A. K. Chao, P. Kapur, E. Morifuji, K. C. Saraswat, Y. Nishi,Electro-Thermally Coupled Power Optimization for Future Transistors and Its Applications, IEEE Trans Electron Devices, Vol. 54, No. 7, pp. 1696-1704, July 2007.
  16. E. Morifuji, D. Patil, M. Horowitz and Y. Nishi, Power Optimization for SRAM and Its Scaling IEEE Trans. Electron Devices Vol.54 No.4, pp715-722, April 2007
  17. K. Tsunoda, Y. Fukuzumi, J.R. Jameson, Z. Wang, P.B. Griffin, and Y. Nishi, Bipolar Resistive Switching in Polycrystalline TiO2 Films Applied Physics Letters Vol.90, pp.113501-1 V 113501-3, March, 2007.
  18. Z. Wang, P.B. Griffin, J. McVittie, S.Wong, P. C. McIntyre, and Y. Nishi, "Resistive Switching Mechanism in ZnxCd1-xS Nonvolatile Memory Devices" IEEE Electron Device Letters Vol.28, pp14-16, January, 2007.
  19. J.R. Jameson, Y. Fukuzumi, K. Tsunoda, P.B. Griffin, G.I. Meijer, and Y. Nishi, Field-Programmable Rectification in Rutile TiO2 Crystals, submitted to Applied Physics Letters 2006.
  20. B. B. Triplett, J. P. T. Chen, Y. Nishi, "Electron Spin Resonance Study of As-Deposited and Annealed (HfO2)x(SiO2)1-x High-k Dielectrics on Si," Journal of Applied Physics, Vol.101, pp.013703-5 January, 2007
  21. J.R. Jameson, W. Harrison, P.B. Griffin, J.D. Plummer, and Y. Nishi, Semiclassical Model of Dielectric Relaxation in Glasses, Journal of Applied Physics Vol.100 (12), pp124104-1 V 124104-20 December, 2006
  22. S. Park, B. Magyari-Kope, L. Colombo, Y. Nishi, and K. Cho, "First Principles Study of Al-Ni Bi-layer Work Function on SiO2, submitted to Journal of Applied Physics, December 2006
  23. M. Makarova, J.Vuckovic, H. Sanda, and Y. Nishi, "Silicon-Based Photonic Crystal Nanocavity Light Emitters Appl. Phys. Letters Vol. 89, pp221101, November, 2006.
  24. H. Jagannathan, Jungyup Kim, Michael Deal, Michael Kelly, Yoshio Nishi, "Halide Passivation of Germanium Nanowires, ECS Transactions, Volume 3, Issue 7, pp. 1175-1180, October 2006.
  25. H. Jagannathan, Y. Nishi, M.Reuter, M. Copel, E. Tutuc, and S. Guha, "Effect of Oxide Overlayer Formation on the Growth of Gold Catalyzed Epitaxial Silicon Nanowires, Applied Physics Letters, Vol. 88, pp103113-1,October, 2006.
  26. J.R. Jameson, P.B. Griffin, J.D. Plummer, and Y. Nishi, "Charge Trapping in High-k Gate Stacks Due to the Bilayer Structure Itself" IEEE Trans. Electron Devices Vol.53, No.8, pp1858-1867, August 2006.
  27. Y. Lu, S. Bangsaruntip, X. Wang, L. Zhang, Y. Nishi, and H. Dai., "DNA Functionalization of Carbon Nanotubes for Ultrathin Atomic Layer Deposition of High K Dielectrics for Nanotube Transistors with 60 mV/Decade Switching", Journal of the American Chemical Society, Vol. 128, No. 11, pp. 3518-3519, November, 2006.
  28. T. Krishnamohan, Z. Krivokapic, K.Uchida, Y.Nishi, and K.Saraswat, "High-Mobility Ultrathin Strained Ge MOSFETs on Bulk and SOI with Low Band-to-Band Tunneling Leakage: Experiments, IEEE Trans. Electron Devices, 53, pp. 990-999, May 2006.
  29. T. Krishnamohan, D. Kim, C.D. Nguyen, C. Jungemann, Y. Nishi, and K. Saraswat, "High Mobility Low Band-to-Band Tunneling Strained Germanium Double gate Heterostructure FETs: Simulations, IEEE Trans. Electron Devices, 53, pp.1000-1009, May 2006
  30. H. Jagannathan, H.-C.Kim, E.M. Freer, L. Sundstrom, T. Topuria, P. M. Rice, M. Deal, Y. Nishi, "Templated Germanium Nanowire Synthesis Using Oriented Mesoporous Organosilicate Thin Films," Journal of Vacuum Science and Technology B 24(5) pp 2220-2228, May 2006.
  31. H. Jagannathan, J. Woodruff, M. Deal, P. C. McIntyre, C. Chidsey, Y. Nishi, "Nature of Germanium Nanowire Heteroepitaxy on Silicon Substrates," Journal of Applied Physics Vol.100, pp. 024318, February 2006
  32. G. Zhang, D. Mann, L. Zhang, A. Javey, Y. Li, E. Yenilmez, Q. Wang, J. McVittie, Y. Nishi, J. Gibbons, and H. Dai, Ultra-High-Yield Growth of Vertical Single-Walled Carbon Nanotubes: Hidden Roles of Hydrogen and Oxygen, PNAS 102 pp.16141, August 2005
  33. C-H .Lu, G. Wong, M. Deal, W. Tsai, P. Majhi, C. O. Chui, M.R. Visokay, J.J. Chambers, L. Colombo, B. M. Clemens and Y. Nishi Characteristics and Mechanism of Tunable Work Function Gate Electrodes Using a Bilayer Metal Structure on SiO2 and HfO2 IEEE Electron Device Letters Vol.26, No.7 pp 445-448, July 2005.
  34. J. Nasrullah, G.L. Tyler and Y. Nishi, An Atomic Force Microscope Study of Surface Roughness of Thin Silicon Films Deposited on SiO2 IEEE Trans. Nanotechnology, Vol. 4 No. 3, pp303-311, May 2005.
  35. Y. Li, D. Mann, M. Roland, W. Kim, A. Ural, S. Hung, A. Javey, J. Cao, D. Wang, E. Yenilmez, Q. Wang, J. Gibbons, Y. Nishi and H. Dai Preferential Growth of Semiconducting Single-Walled Carbon Nanotubes by a Plasma Enhanced CVD Method, Nano Lett., 4, pp.317, April, 2004.
  36. R. R. Doering and Y. Nishi, "Limits of Integrated-Circuit Manufacturing Special Issue on Limits of Semiconductor Technology, Proc. of the IEEE, Vol. 89, pp. 375-393, March 2001.
  37. Nishi, Surface States and Device Performance, (invited) Proc. 8th International Symposium on Silicon Materials Science and Technology, vol. 1, pp. 301-318, May 1998.
  38. Y. Nishi, Research Collaboration in Semiconductor in the United States, (invited) Ohyo Buturi Japan Society of Applied Physics , vol. 66, pp. 827-829, August, 1997.
  39. J. P. Snyder, Y. Nishi and C. R. Helms, Experimental Investigation of a PtSi Source and Drain Field Emission Transistor, Appl. Physics Letters, vol. 67, pp. 1420-1422, September 1995.
  40. Y. Nishi, Challenges in CMOS Technology, Solid State Technology, vol. 31, pp. 115-119, November 1988.
  41. Y. Nishi, Direction of VLSI CMOS Technology, Hewlett Packard Journal, vol. 38, pp. 24-25, June 1987.
  42. H. Iwai, K. Taniguchi, M. Konaka and Y. Nishi, Two Dimensional Nature of Diffused Layers and Certain Limitations in Scaling-Down Coplanar Structure, IEEE Trans. Electron Devices, ED29, pp. 625-630, April 1982.
  43. Y. Nishi, Comparison of New Technologies for VLSI: Possibilities and Limitations, (invited), Microelectronics Journal, vol. 12, pp. 5-14, June 1981.
  44. T. Mochizuki, T. Tsujimaru, M. Kashiwagi and Y. Nishi, Film Properties of MoSi2 and Their Application to Self-Aligned MoSi2 Gate MOSFET, IEEE Trans. Electron Devices, ED27, pp. 1431-1435, August 1980

Blanka Magyari-Köpe

Contact

Office: Paul G. Allen 105
420 Via Palou Mall, Stanford, CA 94305
Phone: 650-725-5725
Webpage: http://www.stanford.edu/~blankamk/indexRes.html
Email: blankamk

Main areas of interest include: the study of interfaces both atomically sharp and with defects (vacancies) and other dopants in multilayer thin films. The characterization based on first principles methods had been limited by size considerations and by the lack of computational models able to tackle this with high accuracy. A new direction that includes electronic transport calculations based on first principles it is currently emerging. Now a direct link between the theoretical description of the fundamental properties can be established to measurable experimental quantities, thus providing a strong interchange between theoretical and experimental data. First principles calculations play a key role through its computational materials design capabilities in testing and proposing possible new materials to be used in direct applications that are better suited, cheaper and/or more stable.

While the types of materials problems amenable to these tools is becoming wider, direct applications are ranging from semiconductors to oxide and metal interfaces, modeling the whole gate stack of a CMOS transistor, understanding the tunneling transistors, contact resistance issues, Schottky barrier modulation, Fermi level de-pinning, bio-censors design, and improving the characteristics of the organic semiconductors.

Lennon Yao Ting Lee

Ph.D candidate in Electrical Engineering
Education: B.S., Electrical Engineering, Columbia University, 2009
Research interests: Semiconductor optoelectronics
Email: lennonl

Jiaomin Ouyang

Ph.D. student in Materials Science and Engineering
Education: B.S., Materials Science and Engineering, University of Florida, 2010
Research Interests: Experimental study of amorphous metal alloys as gate materials for sub-32nm transistors
Email: jouyang

Marjan Aslani

Ph.D candidate in Electrical Engineering
Education: M.S., Electrical Engineering, Stanford University
B.S., Electrical Engineering, The George Washington University, 2009
Research interests: Engineering band gap in graphene, Characterization of electronic properties in graphene, Characterization of electrical and transport properties in graphene, Graphene synthesis.
Email: aslani

Liang Zhao

Ph.D candidate in Electrical Engineering
Education: B.S., Electrical Engineering, Tsinghua University, 2010
Research interests: Simulations and experimental works of transition metal oxide RRAM
Email: lzhao10

Aryan Hazeghi

PhD Candidate, Electrical Engineering
MSc, Electrical Engineering, Stanford, 2012
Bsc, Electrical Engineering, Sharif University, 2010
Email: hazeghi
Resume: Click here.


 Dissertation Topic: Study of Nonvolatile Resistance Change Memory Devices

 I study transition-metal-oxide based nonvolatile memory with focus on Ta2O5 and HfO2. This project is part of the Stanford Nonvolatile Memory Research Initiative program. The memory forming and switching mechanisms are investigated using a novel membrane-based lateral device structure that is optimized for in-situ characterization. Devices are fabricated and characterized using state-of-the-art semiconductor processing and measurement techniques, followed by physics-based and statistical modeling of the experimental data. 
Results: Currently acquiring data from final stage of characterization.

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