Joseph Po-Ta Chen

 
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Office:
CISX 304
 
 
Phone:
(650)725-0417
 
       
Educatiion:
  • Ph.D. in Materials Science and Engineering, Stanford University, CA, USA
    (
    June, 2008)
  • M.S. in Materials Science and Engineering, Stanford University, CA, USA
    (June, 2005)
  • B.S. in Chemical Engineering, National Taiwan University, Taiwan
    (June, 1999)

Thesis Title:

Defects and Bonding Configurations in High-k/Si and High-k/GaAs Gate Structures

Download thesis PDF file-click here

Thesis Abstract:

In order to reduce the gate leakage current while keeping the pace of increasing the gate capacitance to enhance the device performance, higher dielectric constant (k) gate dielectric materials are needed for the next generation CMOS devices. However, the high-k/Si interface defects and oxide charge trapping centers still remain as critical challenges to process optimizations for MOS gate stacks.
In parallel, extending Si-based CMOS technology to III-V MOSFETs is desirable due to the clear device performance advantages in and beyond the 15 nm technology node. However, to achieve the stable and controlled gate dielectrics/III-V interfaces is still challenging since the native oxides of III-V materials are observed to induce high density of interface traps and cause Fermi level pinning.
In the first part of this work, electron spin resonance (ESR) is utilized to characterize interface defects, Pb0 and Pb1, and trapping centers, EX, in MOCVD high-k HfxSi1-xO2 and HfO2 on (100)Si, which are correlated to the interface bonding configurations measured by SRPES and the cross-section TEM images. Mobility degradation in MOSFET devices made with HfxSi1-xO2 dielectrics shows strong correlation with the ESR measured interface defect density. ESR measured density of interface trapped states (ESR-Dit) exhibits distinct charge peaks distributed in the Si band gap and strong relationship to the quality of interfacial layer (IL) in different high-k/Si stacks.
In the second part of this work, the interface between the ALD HfO2 and (100)GaAs chemically treated with the HCl/(NH4)2S cleaning/passivation is studied. SRPES and ESR spectra indicate successful removal of the native oxides, formation of the passivating sulfides on the GaAs surface, and decreasing paramagnetic surface defect density after the chemical treatments. Layer-by-layer removal of the HfO2 film reveals As2O3 formation in the interface during the ALD deposition and after the 450 oC post-deposition anneal. Traces of arsenic and sulfur out-diffusion into the HfO2 film are observed after anneal. TEM images show a thicker HfO2 film for a given precursor exposure on the chemically treated GaAs versus the non-treated sample. The HCl/(NH4)2S treatments appear to provide an effective chemical passivation for GaAs and a superior initial GaAs surface for the ALD HfO2 deposition.

Selected Publications:


Working Experience:

  • Sep 2004 - Jun 2008
    Research Assistant, INTEL High Mobility Device Project, and INMP
    Nanoelectronics Lab, Stanford Univ. and IBM Almaden Research Center

  • Jun 2004 - Aug 2004
    Photolithography R&D Intern Engineer
    Taiwan Semiconductor Manufacturing Co., Ltd. (TSMC)
  • Aug 2002 - Jul 2003
    Lecturer, Physical Chemistry Lab, Department of Chemistry,
    National Taiwan Normal University
  • Oct 2001 - May 2002
    Research Assistant, Surface Material Chemical Analysis Lab,
    National Taiwan University, National Science Council, Taiwan
  • Jul 1999 - April 2001
    2nd Leutenant, Nuclear Biological Chemical Defense Force, Taiwan Army

Awarded Honors:

  • AMAT (Applied Materials) Graduate Student Fellowship, 2005-2008
  • INTEL III-V High Mobility Device Research Assistantship, 2006-2008
               
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