As the minimization of integrated circuits (IC) continues based upon the scaling principle, power consumption and dissipation of heat issues become critical challenges that block the continuation of the Moore's law. In order to minimize the power consumption of future transistors, ultra-shallow junctions (USJ) formation technology is one of the key elements of low-power technology that is used to reduce leakage currents caused by Drain Induced Barrier Lowering (DIBL). As a result, USJ formation and control of the source and drain of MOS transistors become one of the essential components for future high-performance transistor fabrications. With the capability of achieving abrupt doping profiles with adequate sheet resistances, such advanced thermal annealing techniques as rapid thermal annealing (RTA), flash lamp annealing (FLA), laser spike annealing (LSA) become potential candidates for the USJ formation. We study physical mechanisms of USJ formation under millisecond thermal annealing and investigate the behavior of defects with respect to annealing temperature and time. We then incorporate the calibrated shallow junction doping profiles for the source-drain extension (SDE) junctions for the simulation of the ITRS 65nm/45nm high-performance planar single gate and 45nm double-gate (DG) transistors, and characterize optimal device parameter constraints.
Continuous miniaturization of transistors has resulted in a dramatic rise in power dissipation in modern IC chips. Minimization of dynamic power consumption through an adequate design methodology and efficient removal of heat through a novel thermal management are two of the most critical research areas to ensure further scaling of sub-hundred nanometer integrated circuits. The inevitable presence of variations of manufacturing-induced device parameters and also time-dependent fluctuation of the supply voltage not only forces conservative designs but also exacerbates an already severe problem of rising static leakage power. We have developed a novel, electro-thermally coupled, power optimization methodology and proposed a new methodology for a constant-delay-optimization-based design. In addition, with incorporation of the supply voltage, temperature, and process-induced variations, our methodology self-consistently allow us to evaluate the globally optimized total power consumption scheme at the corresponding temperatures as a function of delay for a given set of transistors (bulk, DGFET, FDSOI, PDSOI) at future technology nodes.
