Year 2007-08

Refereed Journal Publications

  1. Jia Feng, Gaurav Thareja, Masaharu Kobayashi, Shulu Chen, Andrew Poon, Yun Bai, Peter B. Griffin, Simon S. Wong, Yoshio Nishi, and James D. Plummer,"High-Performance Gate-All-Around GeOI p-MOSFETs Fabricated by Rapid Melt Growth Using Plasma Nitridation and ALD Al2O3 Gate Dielectric and Self-Aligned NiGe Contacts", IEEE ELECTRON DEVICE LETTERS, VOL. 29, NO. 7, July (2008)
  2. P. T. Chen, B. B. Triplett, P.C. McIntyre, Y. Nishi, et al., " Analysis of Electrically Biased Paramagnetic Defect Centers in HfO2 and HfxSi1-xO2/(100)Si Interfaces", Journal of Applied Physics (JAP), 104, 014106 (2008)
  3. P. T. Chen, Y. Sun, E. Kim, P.C. McIntyre, P. Pianetta, Y. Nishi, et al.," HfO2 gate dielectric on (NH4)2S passivated (100) GaAs grown by atomic layer deposition", Journal of Applied Physics (JAP), 103 , 034106 (2008).
  4. B. B. Triplett, P. T. Chen, Y. Nishi, et al, "Electron spin resonance study of as-deposited and annealed (HfO2)x(SiO2)1-x high-k dielectrics on Si" , Journal of Applied Physics (JAP), 101, 013703 (2007)
  5. B. C. Paul, R. Tu, S. Fujita, M. Okajima, T. Lee, and Y. Nishi, "A Circuit Compatible Analytical Device Model for Nanowire FET," in IEEE Trans. on Electron Devices (TED), vol. 54, n 7, pp. 1637-1644, July, 2007.
  6. B. C. Paul, S. Fujita, M. Okajima, T. Lee, H. S. P. Wong, and Y. Nishi, "Impact of Process Variation on Nanowire and Nanotube Device Performance," in IEEE Trans. on Electron Devices, vol. 54, n 9, pp. 2369-2376, September, 2007.
  7. B. C. Paul, R. Tu, S. Fujita, M. Okajima, Y. Nishi, and T. Lee, "A Circuit Compatible Analytical Device Model for Nanowire FET Considering Ballistic and Drift-Diffusion Transport," in NANOTECH, vol. 3, pp. 692-695, 2007.
  8. B. C. Paul, S. Fujita, M. Okajima, T. Lee, H. S. P. Wong, and Y. Nishi, "Impact of process variation on Nanowire and Nanotube Circuit Performance,"in DRC, pp. 269-270, 2007.
  9. Li Geng, Blanka Magyari-Kope, Zhiyong Zhang, and Yoshio Nishi, Ab initio Modeling of Schottky Barrier Height Tuning by Yttrium at Nickel Silicide/Silicon Interface, IEEE Electron Device Letters, 2008, accepted for publication.
  10. Blanka Magyari-Kope, Seongjun Park, Luigi Colombo, Yoshio Nishi, and Kyeongjae Cho, First Principles Study of Effective Work Function Modulation on SiO2, to be submitted to Journal of Applied Physics.
  11. Z. Liu, H. A. Becerril, M. E. Roberts, Y. Nishi and Z. Bao, “High Performance Air-Stable Solution Processed Organic Field Effect Transistors based on an Asymmetric Oligothiophene”, Applied Physics Letters, in preparation.
  12. H. A. Becerril, M. E. Roberts, Z. Liu, J. Locklin and Z. Bao, “High-Performance Organic Thin Film Transistors through Solution Sheared Deposition of Small Molecule Organic Semiconductors”, Advanced Materials, 2008, accepted (in press).

Conference Presentations:

  1. Masaharu Kobayashi, Atsuhiro Kinoshita, Krishna Saraswat, H. -S. Philip Wong and Yoshio Nishi,"Fermi-Level Depinning in Metal/Ge Schottky Junction and Its Application to Metal Source/Drain Ge NMOSFET" Symposium on VLSI Technology, 2008, session 6.2, Tuesday, June 17, 3:50 p.m., Hawaii, USA
  2. Masaharu Kobayashi, Po-Ta Chen, Steven Sun, Niti Goel, Mike Garner, Wilman Tsai, Piero Pianetta and Yoshio Nishi,"Interface analysis between ALD high-k HfO2 and InGaAs, InAlAs",European Materials Research Society, 2008, session 14.5, May 30, 11:00 a.m., Strasbourg, France
  3. Masaharu Kobayashi, Atsuhiro Kinoshita, Krishna Saraswat, H. -S. Philip Wong and Yoshio Nishi,"Novel Metal/Ge Contact Technology for Metal Source/Drain Ge Transistor Application",the 214th ECS Meeting, 2008
  4. Masaharu Kobayashi, Thareja Gaurav, Yasuhiro Oshima, Jim McVitee, Peter Griffin, and Yoshio Nishi,"High Quality Interfacial GeO2 Processed by High-Density Plasma in Ge High-k Gate stack",the 214th ECS Meeting, 2008
  5. P. T. Chen, B. B. Triplett, Y. Nishi, J. Chambers, et al., "Effect of electrical bias on paramagnetic defects at high-k (HfO2)x(SiO2)1-x on (100)Si, 38th Semiconductor Interface Specialists Conference (SISC), Washington D.C., p.1 (2007).
  6. P. T. Chen, B. B. Triplett, Y. Nishi, et al., "Electron spin resonance study of as-deposited and annealed (HfO2)x(SiO2)1-x high-k dielectrics on Si", Silicon Nanoelectronics Workshop (SNW), Kyoto, Japan, p.53 (2007).
  7. P. T. Chen, Y. Sun, P.C. McIntyre, P. Pianetta, Y. Nishi, et al., "Interface analysis Between ALD high-k HfO2 and sulfur passivated GaAs", Mat. Res. Soc. Symp., H4.3, San Francisco, USA, Spring (2007)
  8. Blanka Magyari-Kope, Yoshio Nishi, and Kyeongjae Cho, Effective Work Function Control by Metal-Oxide Interface Characteristics, MRS, Spring Meeting, San Francisco, 2008.
  9. Z. Liu, H. A. Becerril, M. E. Roberts, Y. Nishi and Z. Bao, “High-Performance Air-Stable Solution Processed Organic Transistors”, Oral Presentation, 66th Annual Device Research Conference (DRC), Santa Barbara, CA, Jun. 23-25, 2008.
  10. Z. Liu, H. A. Becerril, M. E. Roberts, Y. Nishi and Z. Bao, “High-mobility Air-stable Solution-Shear-Processed Organic Transistors based on an Asymmetric Small Molecule for Flexible Electronic Applications”, Oral Presentation, Materials Research Society (MRS) Spring Meeting, San Francisco, CA, Mar. 24-28, 2008. (won First-Prize “Science as Art” Award)
  11. Z. Liu, H. A. Becerril, M. E. Roberts, Y. Nishi and Z. Bao, “Solution-Processed Organic Transistors and Circuits for Flexible Electronics”, CIS AdCom Fall Meeting, Stanford, CA, Nov. 14, 2007.
  12. Sung-Woo Kim and Yoshio Nishi, "Copper sulfide-based resistance change memory", Non-Volatile Memory Technology Symposium, 2007, Albuquerque
  13. Sung-Woo Kim, Oun-Ho Park, Ho-Cheol Kim and Yoshio Nishi, "Cu2-xS nanopillar arrays grown in self-assembled diblock copolymer templates", NMTRI Review Meeting, 2007, Stanford
  14. Sung-Woo Kim and Yoshio Nishi, "Effects of heat treatment on switching properties of copper sulfide", NMTRI Review Meeting, 2007, Stanford
  15. Gaurav Thareja, Masaharu Kobayashi, Yasuhiro Oshima, James McVittie, Peter Griffin and Yoshio Nishi, "High Quality Interfacial Layer using High-Density Plasma Oxidation in Germanium High-k Gate stack", Device Research Conference, 2008

Year 2006
Invited Papers

  1. T. Krishnamohan, Z. Krivokapic, K.Uchida, Y.Nishi, and K.Saraswat, "High-Mobility Ultrathin Strained Ge MOSFETs on Bulk and SOI with Low Band-to-Band Tunneling Leakage: Experiments," IEEE Trans. Electron Devices, 53, 990-999, 2006
  2. T. Krishnamohan, D. Kim, C.D. Nguyen, C. Jungemann, Y. Nishi, and K. Saraswat, "High Mobility Low Band-to-Band Tunneling Strained Germanium Double gate Heterostructure FETs: Simulations", IEEE Trans. Electron Devices, 53, 1000-1009, 2006

Plenary/Invited Presentations

  1. Yoshio Nishi, "Current Trends and Status of Nanoelectronic Devices"2005 SINANO Workshop, September, 2005, Grenoble, France
  2. Yoshio Nishi"Technological Innovations Learned in Integrated Circuits and Nanoelectronics" Innovation Symposium February 4, 2006 AIST, Japan
  3. Yoshio Nishi, "Nanoelectronic Materials and Processes, National Nanotechnology Infrastructure Network and Nanomanufacturing "ERC/SRC Review, University of Arizona, Tucson, AZ, Feb.23-24,2006
  4. Yoshio Nishi,"Nanoelectronic Materials and Devices as New Opportunity"2006 IEEE NMDC, October 23-25, 2006, Geyongju, Korea
  5. Yoshio Nishi, "Scaling Limit of Silicon and non-Silicon Opportunities" FTM 2006 Workshop, June 26-30, 2006, Crete, Greece
  6. Yoshio Nishi, " Challenges of Nanoelectronic Devices and Materials" 2005 Symposium on Nanoscale Materials, Processes and Devices,
    November 3-4, 2005, Hapuna Beach Prince Hotel, Hawaii
  7. Yoshio Nishi, "Semiconductor Technology, Past, Present and Future" ISESH2005, September, 2005, Portland, Oregon
  8. Paul McIntyre and Yoshio Nishi, "Ferroelectric Nonvolatile Memories: Opportunities, Progress and Challenges" The 17th International Symposium on Integrated Ferroelectrics, April, 17, 2006, Shanghai, China
  9. Yoshio Nishi, "Industry-Academia Collaboration for Nanotechnology Research" 2006 Japan NANOET Symposium, February 20,21 Tokyo, Japan
  10. Yoshio Nishi, "Trends in Three Dimensional Integration Research and Development in US" Kumamoto Colloquium, February 2, 2006, Japan
  11. Yoshio Nishi, "Trends of IC Technology Research and Opportunities in Nanoelectronics" Kumamoto Semiconductor Forest Forum, February3, 2006, Japan
  12. Yoshio Nishi, "Nanoelectronic Materials and Devices" Materials Integrity Management Symposium, June 6-7, 2006, Stanford
  13. Yoshio Nishi, "Where Will CMOS Scaling and Non-Silicon Opportunities Go?" Nano Korea 2006,August 30-September 1, Kintex, Korea
  14. Yoshio Nishi, "CMOS Scaling and Non-Silicon Opportunities"NanoCMOS Workshop, Jan. 30-Feb.1, 2006 Mishima, Japan
  15. Yoshio Nishi, "Nanoelectronics and its Future" NEC Technology Forum, April 13-14, 2006, Tokyo
  16. Yoshio Nishi,"Silicon Nanoelectronics, Past, Today and Future"2006 Silicon Nanoelectronics Workshop, Hilton Village, Honolulu

Books and Contributions to Books

1. H. Iwai, Y. Nishi, M.S. Shur and H.Wong, "Frontiers in Electronics" World Scientific, New Jersey, 2006

Refereed Journal Publications

  1. Hemanth Jagannathan, Ho-Cheol Kim, Erik M. Freer, Linnea Sundstrom, Teya Topuria, Philip M. Rice, Michael Deal, Yoshio Nishi, "Templated Germanium Nanowire Synthesis using Oriented Mesoporous Organosilicate Thin Films," Journal of Vacuum Science and Technology B 24(5) 2220, 2006.
  2. Hemanth Jagannathan, Jacob Woodruff, Michael Deal, Paul C. McIntyre, Christopher Chidsey, Yoshio Nishi, "Nature of Germanium Nanowire Heteroepitaxy on Silicon Substrates," Journal of Applied Physics 100, 024318, 2006.
  3. Hemanth Jagannathan, Yoshio Nishi, Mark Reuter, Matthew Copel, Emanuel Tutuc, and Supratik Guha, "Effect of oxide overlayer formation on the growth of gold catalyzed epitaxial silicon nanowires," Applied Physics Letters, Vol. 88, 2005.
  4. Maria Makarova, Jelena Vuckovic, Hiroyuki Sanda, and Yoshio Nishi, " Silicon-based photonic crystal nanocavity light emitters" Appl. Phys. Lett. 89, 221101 (2006)
  5. Seongjun Park, Blanka Magyari-Kope, Luigi Colombo, Yoshio Nishi, and Kyeongjae Cho, First Principles Study of Al-Ni Bi-layer Work Function on SiO2, submitted to Journal of Applied Physics, December, 2006.
  6. J.R. Jameson, Y. Fukuzumi, K. Tsunoda, P.B. Griffin, and Y. Nishi, "Observation of field-programmable rectification in rutile TiO2 crystals,"submitted to Applied Physics Letters (2006)
  7. K. Tsunoda, Y. Fukuzumi, P.B. Griffin, Z. Wang, J.R. Jameson, and Y. Nishi, "Bipolar resistive switching in polycrystalline TiO2 films,"submitted to Applied Physics Letters (2006)
  8. B. B. Triplett, P. T. Chen, Y. Nishi, P.H. Kasai, J. J. Chambers and L. Colombo, "Electron spin resonance study of as-deposited and annealed (HfO2)x(SiO2)1-x high-k dielectrics on Si", Journal of Applied Physics, Vol.100, 2006
  9. Kim, W; Javey, A; Tu, R; Cao, J; Wang, Q; Dai, HJ, " Electrical contacts to carbon nanotubes down to 1 nm in diameter" Applied Phys. Letters; Oct. 24 2005; v.87, no.17, p.173101
  10. Zhang, L; Tu, R; Dai HJ, "Parallel Core-Shell Metal-Dielectric-Semiconductor Germanium Nanowires for High-Current Surround-Gate Field-Effect Transistors", Nano Letters, in press
  11. J.R. Jameson, P.B. Griffin, J.D. Plummer, and Y. Nishi, "Charge trapping in high-k gate stacks due to the bilayer structure itself" IEEE Transactions on Electron Devices 16 (53), 1858-1867 (2006)
  12. J.R. Jameson, W. Harrison, P.B. Griffin, J.D. Plummer, and Y. Nishi, "A Semiclassical Model of Dielectric Relaxation in Glasses," Journal of Applied Physics 100, 1 (2006)
  13. Zheng Wang, Peter B. Griffin, Jim McVittie, Simon Wong, Paul C. McIntyre, and Yoshio Nishi, "Resistive Switching Mechanism in ZnxCd1-xS Nonvolatile Memory Devices" IEEE Electron Device Letters 28 (2007), January.

    Conference Presentations:
  14. J.R. Jameson, Y. Fukuzumi, H.-C. Kim, and Y. Nishi,O3.2 "Resistance-change memory from nanoscale volumes of metal sulfides fabricated using self-assembled di-block copolymers," to be presented at 2006 Materials Research Society Fall Meeting, November 27-31, Boston, MA, USA
  15. J.R. Jameson and Y. Nishi, "Charge trapping in high-k gate stacks due to the bilayer structure itself," 2006 IEEE International Integrated Reliability Workshop, October 16-19, Fallen Leaf Lake, CA, USA (poster)
  16. P.T. Chen, B. B. Triplett, Y. Nishi, P.H. Kasai, J. J. Chambers and L. Colombo, "Electron spin resonance study of as-deposited and annealed (HfO2)x(SiO2)1-x high-k dielectrics on Si", 37th Semiconductor Interface Specialists Conference (SISC), San Diego, California, USA, December 2006
  17. H. Sanda, J. McVittie, M. Koto, K. Yamagata, T. Yonehara, Y. Nishi, "Fabrication and characterization of CMOSFETs on porous silicon for novel device layer transfer", IEDM 2005, Dec. 2005, 679 - 682, Washington D.C.
  18. M. Makarova, J. Vuckovic, H. Sanda, Y. Nishi, "Two-Dimensional Porous Silicon Photonic Crystal Light Emitters", CLEO 2006, June. 2006, Long Beach
  19. New Uses of ESR for Nanoelectronic Materials, Interfaces, and Devices. Baylor Triplett, Peter Peumans, and Yoshio Nishi (invited), 48th Rocky Mountain Conference on Analytical Chemistry, Breckenridge, Colorado, USA, July 2006
  20. Blanka Magyari-Kope, Seongjun Park, Luigi Colombo, Yoshio Nishi, and Kyeongjae Cho, Theoretical Investigation of Metal Work Functions on SiO2 Gate Dielectric, 3rd International Symposium on Advanced Gate Stack Technology, Austin, Texas, September 27-29, 2006.
  21. Jacob Huffman Woodruff, Joshua Ratchford, Hemanth Jagannathan, Yoshio Nishi and Christopher Chidsey, "Deterministic Nanowire Growth" MRS Fall Meeting, Boston, November, 2006.
  22. Hemanth Jagannathan, Jungyup Kim, Michael Deal, Michael Kelly, Yoshio Nishi, "Halide Passivation of Germanium Nanowires," ECS Transactions, Volume 3, Issue 7, pp. 1175-1180, 2006.
  23. Hemanth Jagannathan, Jacob Woodruff, Michael Deal, Paul McIntyre, Christopher Chidsey & Yoshio Nishi, "Nucleation and Growth of Hetero-Epitaxial Germanium Nanowires," Conference on Crystal Growth and Epitaxy, June 2006.
  24. Hemanth Jagannathan, Ho-Cheol Kim, Erik M. Freer, Linnea Sundstrom, Teya Topuria, Philip M. Rice, Michael Deal, Yoshio Nishi, "Low Temperature Template Synthesis of Germanium Nanowires for 3-D Integration," Silicon Nanoelectronics Workshop, June 2006.
  25. Hemanth Jagannathan, Jacob Woodruff, Michael Deal, Paul McIntyre, Christopher Chidsey & Yoshio Nishi, "Controlled Hetero-Epitaxial Synthesis of Germanium Nanowires on Silicon Substrates," 2005 Symposium on Nanoscale Materials, Processes and Devices, December 2005.
  26. J. Woodruff, J. Ratchford, H. Jagannathan, H. Adhikari, H.-S.P. Wong, C.E.D. Chidsey, "Deterministic Nanowire Growth," SRC Techcon, October 2005.
  27. H. Jagannathan, H. Kim, M. Deal, P. C. McIntyre and Y. Nishi, "Analysis of Structure and Orientation of Vertical Germanium Single Crystal Nanowires on Silicon Substrates," Solid State Devices and Materials, Kobe, Japan, September 2005.
  28. Hemanth Jagannathan, Hyoungsub Kim, Michael Deal, H.-S. Philip Wong, Paul McIntyre, Christopher Chidsey & Yoshio Nishi, "Low Temperature Heteroepitaxial Synthesis and Control of Germanium Nanowires on Silicon Substrates," First Internatioanl Nanotechnology Conference on Communication and Cooperation, June 2005.
  29. Rong Chen, David W. Porter, Hyoungsub Kim, Paul C. McIntyre, Hemanth Jagannathan, Yoshi Nishi and Stacey F. Bent, "Area-Selective Atomic Layer Deposition for in-situ Gate Stack," MRS Conference, March 2005.
  30. S. -W. Kim, P. Griffin, H. -S. Wong, S. Wong, P. McIntyre, and Y. Nishi, "Cu2S-Based Conductance Bridge Memory", in NMTRI, May, 2006.
  31. S. -W. Kim, O. -H. Park, J. Jameson, P. Griffin, H. -C. Kim, and Y. Nishi, "Block Copolymer Templates for Nanopatterning of Cu2S", in NMTRI, Nov. , 2006
  32. J. Jameson, Y. Fukuzumi, H. -C. Kim, J. Cheng, O. -H. Park, S. -W. Kim, and Y. Nishi, "Resistance-change memory from nanoscale volumes of metal sulfides fabricated using self-assembled di-block copolymers", in MRS, Nov. , 2006, Boston.
  33. C-H. Lu, G. Wong, R. Birringer, M. Deal, B. Clemens, and Y. Nishi, "Work Function Tuning and Device Characteristics of Bilayer Metal Gate Stacks," IEEE 3rd International Symposium on Advanced Gate Stack (ISAGST), Austin, TX, USA, Sep. 27-29, 2006
  34. C-H. Lu, G. Wong, M. Deal, B. Clemens, and Y. Nishi, "Thermal Stability and Device Characteristics of MOSFETS Utilizing Bilayer Metal Gates for Threshold Voltage Control," Mat. Res. Soc. Symp., E8.3, San Francisco, USA, Apr. 17-21, 2006.
  35. G. M. T. Wong, C-H. Lu, M. Deal, Y. Nishi, and B. M. Clemens, " Work Function Behavior of Nb-W and Ti-W Bilayer Metal Gates via Physical Characterization and Diffusion Modeling", IEEE 3rd International Symposium on Advanced Gate Stack (ISAGST), Austin, TX, USA, Sep. 27-29, 2006
  36. G. Wong, C-H. Lu, M. Deal, Y. Nishi, B. Clemens, "Diffusion Modeling and the Effect of Alloy Composition on Work Function of Metal Gate Electrodes," Mat. Res. Soc. Symp., E8.5, San Francisco, USA, Apr. 17-2, 2006.
  37. J. Kim, J. McVittie, K. Saraswat and Y. Nishi, "Passivation Studies of Germanium Surface", 8th International Symposium on Ultra Clean Processing of Silicon Surfaces, Sep. 18th-20th 2006, Antwerp, Belgium.
  38. J. Kim, J. McVittie, K. Saraswat and Y. Nishi, "Germanium Surface Cleaning with
    Hydrochloric Acid", ECS Transactions; v.3, no.7, p.1191-1196 (2006), Cancun, Mexico.
  39. H. Jagannathan, J. Kim, M. Deal, M. Kelly, Y. Nishi, "Halide
    Passivation of Germanium Nanowires", ECS Transactions; v.3, no.7, p.1175-1180 (2006),Cancun, Mexico.
  40. J. Kim, K. Saraswat and Y. Nishi, "Study of germanium surface in wet chemical solutions for
    surface cleaning applications", ECS Transactions; v.1, no.3, p.214-219 (2005), Los Angeles,
    CA.

Year 2005

Invited talks by Prof. Yoshio Nishi

  1. "Current Trends and Status of Nanoelectronic Devices"(plenary talk), 2005 Silicon Nanoelectronics, SINANO, Workshop, Grenoble, France, September, 2005.
  2. "CMOS Scaling and Nanoelectronics: New Materials and Processes Beyond Silicon"(plenary talk) Electrochemical Society Meeting, Quebec City, May, 2005.
  3. "Semiconductor Technology, Past, Present and Future"(keynote address) International Semiconductor Environmental Safety and Health Conference, Portland, Oregon, June, 2005.
  4. "Ferroelectric Nonvolatile Memories: Opportunities and Challenges" (plenary talk) 17 th International Symposium on Integrated Ferroelectrics, Shanghai, China, April, 2005.
  5. "Nanoelectronic Materials and Devices, Challenges and Opportunities"(keynote address) STM 2005, Hokkaido, Japan, July, 2005.
  6. "Nanoscale Science and Engineering, What is it and where can it contribute?" (public lecture), City of Sapporo, Hokkaido, Japan, July, 2005.
  7. "Nanoelectronics Research Trends and National Nanotechnology Infrastructure Network" (plenary talk), Workshop of Future of Electronics", WOFE, Aruba, December, 2004.
  8. "CMOS Scaling and Nanoelectronics Era" (keynote address) InterPACK, San Francisco , July 2005.
  9. "Challenges of Nanoelectronic Devices and Materials" 2005 Symposium on Nanoscale Materials and Processes, Hawaii, November 2005.
  10. "CMOS Scaling Limits and Nanoelectronic Materials and Devices" IEEE EDS Boise Distinguished Lecture Series, August 2005.
  11. "Nanotechnology and its Implication to Semiconductor Devices" 43 rd Planarization CMP and Application Technology Meeting, Tokyo , April 2005.
  12. "Evolution in Academia-Industry Collaborative System in Nanotechnology Era" ASMeW Symposium, Waseda Univ. , Tokyo , March 2005.
  13. "CMOS Scaling Limits and Nanoelectronic Devices" IEEE Distinguished Lecture Series, Santa Clara, CA, April, 2005.
  14. "Stanford Nanofabrication Facility in National Nanotechnology Infrastructure Network" IEEE South Bay Nanotechnology Conference, March 2005.

 

 Students papers and Conference presentations

  1. H. Jagannathan, J. Woodruff, M. Deal, P. C. McIntyre, C. Chidsey, Y. Nishi, "Nature of Germanium Nanowire Heteroepitaxy on Silicon Substrates," (Under review).
  2. H. Jagannathan, H. C. Kim, E. M. Freer, L. Sundstrom, T. Topuria, P. M. Rice, M. Deal, Y. Nishi, "Templated Germanium Nanowire Synthesis using Oriented Mesoporous Organosilicate Thin Films," (Under review).
  3. H. Jagannathan, Y. Nishi, M. Reuter, M. Copel, E. Tutuc, and S. Guha, "Effect of oxide overlayer formation on the growth of gold catalyzed epitaxial silicon nanowires," Applied Physics Letters, Vol. 88, 2006.
  4. Y. Lu, S. Bangsaruntip, X. Wang, L. Zhang, Y. Nishi, and H. Dai* "DNA Functionalization of Carbon Nanotubes for Ultrathin Atomic Layer Deposition of High K Dielectrics for Nanotube Transistors with 60 mV/Decade Switching " Journal of the American Chemical Society, Vol. 128  No. 11, 2006, page 3518-3519.
  5. H. Sanda, J. McVittie, M. Koto, T. Yonehara, and Y. Nishi, "Fabrication and characterization of NMOS transistors on porous silicon for a novel device layer transfer", IMFEDK05, Kyoto , Japan April 2005.
  6. H. Sanda, J. McVittie, M. Koto, K. Yamagata, T. Yonehara, Y. Nishi, "Fabrication and characterization of CMOS transistors on porous silicon for novel device layer transfer", 2005 IEDM Technical Digest , Washington DC, USA, December 2005.
  7. H. Jagannathan, H. C. Kim, E. M. Freer, L. Sundstrom, T. Topuria, P. M. Rice, M. Deal, Y. Nishi, "Low Temperature Template Synthesis of Germanium Nanowires for 3-D Integration," (To be presented at the Silicon Nanoelectronics Workshop, June 2006).
  8. H. Jagannathan, J. Woodruff, M. Deal, P. McIntyre, C. Chidsey & Y. Nishi, "Controlled Hetero-Epitaxial Synthesis of Germanium Nanowires on Silicon Substrates," 2005 Symposium on Nanoscale Materials, Processes and Devices, December 2005.
  9. J. Woodruff, J. Ratchford, H. Jagannathan, H. Adhikari, H.-S.P. Wong, C.E.D. Chidsey, "Deterministic Nanowire Growth," SRC Techcon, October 2005.
  10. H. Jagannathan, H. Kim, M. Deal, P. C. McIntyre and Y. Nishi, "Analysis of Structure and Orientation of Vertical Germanium Single Crystal Nanowires on Silicon Substrates," Solid State Devices and Materials, Kobe, Japan, September 2005.
  11. H. Jagannathan, H. Kim, M. Deal, H.-S.P. Wong, P. McIntyre, C. Chidsey & Y. Nishi, "Low Temperature Heteroepitaxial Synthesis and Control of Germanium Nanowires on Silicon Substrates," First Internatioanl Nanotechnology Conference on Communication and Cooperation, June 2005.
  12. R. Chen, D. W. Porter, H. Kim, P. C. McIntyre, H. Jagannathan, Y. Nishi and S. F. Bent, "Area-Selective Atomic Layer Deposition for in-situ Gate Stack," MRS Conference, March 2005.
  13. C-H Lu, G. M. T. Wong, M. D. Deal, W. Tsai, P. Majhi, C. O. Chui, M. R. Visokay, J. J. Chambers, L. Colombo, B. M. Clemens, and Y. Nishi, " Characteristics and Mechanism of Tunable Work Function Gate Electrodes Using a Bilayer Metal Structure on SiO 2 and HfO 2," IEEE Electron Device letter, vol. 26, no. 7, pp. 445-447, 2005.
  14. C-H. Lu, G. Wong, M. Deal, S. Hung, S. Park, P. Majhi, W. Tsai, P. McIntyre, B. Clemens, and Y. Nishi, " Bilayer Metal Structure for Tunable Workfunction Gate Electrodes," Mat. Res. Soc. Symp., San Francisco, Spring 2005.
  15. G. Wong, C-H Lu, M. Deal, B. Clemens, Y. Nishi, M. Visokay, J. Chambers , and L. Colombo, " Determination of minimum layer thickness needed to change the work function in a metal bilayer MOS structure," Mat. Res. Soc. Symp., San Francisco, Spring 2005.
  16. S. C. H. Hung, K. Ahmed, C. Olsen, R. Wong, F. Wu, N. Krishna, G. Miner, C-H. Lu, M. Deal and Y. Nishi, " Improved Workfunction Tunability and EOT Control with Clustered ALD TaN/PVD Ta for Multilayer Metal Gate," Mat. Res. Soc. Symp., San Francisco, Spring 2005.
  17. A. K. Chao, P. Kapur, R. S. Shenoy, Y. Nishi, and K.C. Saraswat, "Incorporation of Supply Voltage and Process Variations in the Power Optimization for Future Transistors", Device Research Conference, Santa Babara, CA, 2005.
  18. E. Morifuji, P. Kapur, A. K. Chao, and Y. Nishi, "New Constraint for Vth Optimization for Sub 32nm Node CMOS Gate Scaling," 2005 IEDM Technical Digest.
  19. A. K. Chao, P. Kapur, and Y. Nishi, "Electro-Thermally Coupled Global Power Optimization for Future Transistors", Design Automation Conference, 2006. (Submitted)
  20. K. Uchida, T. Krishnamohan, K.Saraswat and Y. Nishi, "Physical Mechanisms of Electron Mobility Enhancement in Uniaxial Stressed MOSFETs and Impact of Uniaxial Stress Engineering in Ballistic Regime" 2005 IEDM Technical Digest pp.135.
  21. A. Pethe, T. Krishnamohan, D. Kim, S. Oh, H.S. P. Wong, Y. Nishi and K. Saraswat, "Investigation of the Performance limits of III-V Double-Gate n-MOSFETs" 2005 Technical Digest pp.619.
  22. T. Krishnamohan, Z. Krivokapic, K. Uchida, Y. Nishi and K. Saraswat, "Low Defect Ultra-thin Fully Strained-Ge MOSFET on Relaxed Si with High Mobility and Low Band-to-Band Tunneling" 2005 Symposium on VLSI Technology, Kyoto , Japan , June 2005.
  23. G. Zhang, D. Mann, Li Zhang, A. Javey, Y. Li, E. Yenilmez, Q. Wang, J. McVitti, Y. Nishi, J. Gibbons, H. Dai,"Ultra-High-Yield Growth of Vertical Single-Walled Carbon nanotubes: Hidden Roles of Hydrogen and Oxygen" PNAS 102 16141, 2005.
  24. J. Kim, J. McVittie, T. Homma, K. Saraswat and Y. Nishi, "Nanoscopic Charaterization of Ge Single Crystal Surfaces to Develop Environmentally Benign Chemical Treatment for Manufacturing Ge-Based Devies", ERC Review 2005 Poster, Feb 05, Tucson, Arizona.
  25. J. Kim, K. Saraswat and Y. Nishi, "Study of germanium surface in wet chemical solutions for surface cleaning applications", ECS Transactions; 2005; v.1, no.3, p.214-219 (2005).
  26. A. Javey, R. Tu, D.B. Farmer, J.Guo, R.G. Gordon, H. Dai, "High performance n-type carbon nanotube field-effect transistors with chemically doped contacts" Nano Letters; Feb. 2005; vol.5, no.2, p.345-8.
  27. W. Kim, A. Javey, R. Tu, J. Cao, Q. Wang, H. Dai, "Electrical contacts to carbon nanotubes down to 1 nm in diameter" Applied Physics Letters; Oct 24 2005; v.87, no.17, p.1-3.
  28. Y.M. Li, S. Peng, D. Mann, J. Cao, R. Tu, K.J. Cho, H. Dai, "On the origin of preferential growth of semiconducting single-walled carbon nanotubes" Journal of Physical Chemistry B; Apr 21 2005; v.109, no.15, p.6968-6971.
  29. D. Wang, R. Tu, L. Zhang, H. Dai, "Deterministic one-to-one synthesis of germanium nanowires and individual gold nanoseed patterning for aligned nanowire arrays" Angewandte Chemie - International Edition; May 6 2005; v.44, no.19, p.2925-2929.

 

Year 2004

Invited talks by Prof. Yoshio Nishi
  1. ISNM 2004, November 3-5, 2004, KAIST, Korea National Nanotechnology Infrastructure Network, NNIN, and Implications to Nanotechnology Research
  2. 2004 PEUG Symposium, American Vacuum Society, October 15, 2004. Nanoelectronic Materials and Devices beyond CMOS Scaling
  3. IMFEDK 2004, July 26, 2004, Kyoto, Japan. Present and Future of Nanoelectronics Technology Challenges
  4. SRC-NASA Workshop on Novel Materials & Assembly Methods. Practical Requirements and Opportunities for Useful Nanostructures to Extend CMOS Scaling
  5. ICYS 2004, June 1, 2004, Tokyo, Japan. Education/Training/Mentoring and Evaluation of Young Scientists and Engineers in US
  6. International Workshop for Dielectric Thin Films for Future ULSI Devices: Science and Technology, NationalMuseum or Emerging Science and Innovation, Tokyo, May 26, 2004
  7. 6th IEEE/NAETA Annual Conference Semiconductors to Nanotechnology, April 17, 2004, Braun Auditorium, StanfordUniversity. IC Technology, Past, Present and Future, and the Needs for Microelectronics to Nanoelectronics.
  8. ASPRONC 2004, February 4, 2004, Tokyo, Japan. R&D Systems for High Technology Industry. Semiconductor Industry and University Partnership.
  9. Seminar for KumamotoSemiconductorForest, February 2, 2004, Kumamoto. Recent Trends of Semiconductor Industry and Technology Paradigm.
  10. IGNOIE-COE03, January 29-30, 2004, TohokuUniversity. Microelectronics to Nanoelectronics.

     

Books and Contributions to Books

 

Future Challenges and Needs for Nano-electronics from Manufacturing Viewpoint , John Wiley, New York (2004).

 

Students papers and Conference presentations

  1. Y. Li, D. Mann, M. Rolandi, W. Kim, A. Ural, S. Hung, A. Javey, J. Cao, D. Wang, E. Yenilmez, Q. Wang, J. F. Gibbons, Y. Nishi, and H. Dai, "Preferential Growth of Semiconducting Single-Walled Carbon Nanotubes by a Plasma Enhanced CVD Method," Nano Letters, Vol. 4, Issue 2, pp.317-321, February 2004.
  2. K. Uchida, R. Zednik, C-H Lu, H. Jagannathan, J. McVittie, P. McIntyre and Y. Nishi "Experimental Study of Biaxial and Uniaxial Strain Effects on Carrier Mobility in Bulk and Ultrathin-body SOI MOSFET," IEDM 2004.
  3. C. S. Olsen, P. Kraus, K. Ahmed, S. Kher, S. Hung, N. Krishna, C-H. Lu, M. Deal, Y. Nishi: Tunable Workfunction with TaN Metal gate on HfO2-HfSiO Dielectrics, 2004 MRS, San Francisco.
  4. P. Kapur, R.S. Shenoy, A.K. Chao, Y. Nishi, and K.C. Saraswat, "Power Optimization for Future Transistors and A Resulting Global Comparison Standard," IEDM, 2004.

Year 2003

  1. S. Hung, J. Hoyt, J. Gibbons, C-H Lu, M. Deal and Y Nishi: Multilayer Metallic gate electrode for Depletion Suppression and Tunable Workfunction, 2003 SISC, Washington, DC.

  2. Y. Nishi, "Nano-Scale Manufacturing, Challenges for Cost and Reproducibility," Japan-US Nanotechnology Symposium, January 22-24, 2003, Cornell University.

  3. Y. Nishi, "Future of Integrated Circuits Technology for the Internet Era," SASIMI, The 11th Workshop on Synthesis and System Integration of Mixed Information Technologies, April 3, 2003 , Hiroshima University , Japan.
  4. Y. Nishi, "Future Challenges and Needs for Nano-Electronics from Manufacturing View Point," First International Symposium on Nano-Manufacturing, MIT, April 24-26, 2003.
  5. Y. Nishi, "Microelectronics to Nanoelectronics," Stanford Summer Course for Nanotechnology, August 20, 2003.
  6. Y. Nishi, "Micro/Nanoelectronics, Past, Today and Future," 2003 VMIC, September 23, 2003 , Marina del Rey.
  7. Y. Nishi, "Microelectronics to Nanoelectronics," IEEE EDS Santa Clara Valley Chapter Meeting, October 4, 2003.
  8. Y. Nishi, "CMOS Scaling Limits and Opportunity for Nanoelectronics," Advanced Metallization Conference, October 21, 2003 , Montreal , Canada.
  9. Y. Nishi, "A Thought for Industry-Academia Collaboration for Nanotechnology Research and Productization," Science & Engineering Policy Seminar, October 26, 2003, Ministry of Education, Japan
  10. Y. Nishi, "CMOS Scaling Limits and Opportunity for Nanoelectronics," AVS 50th Anniversary Conference, November 3-6, 2003 , Baltimore, MD.
  11. Steven C. H. Hung, Judy Hoyt, James Gibbons, Ching-Huang Lu, Mike Deal and Yoshio Nishi, "Multilayer Metallic Gate Electrode for Depletion Suppression and Tunable Workfunction," 2003 Semiconductor Interface Specialists Conference, Washington, D.C., December 2003.
  12. Y. Nishi, "Technology Roadmap and Beyond," 2003 International Microprocesses and Nanotechnology Conference, MNC, 2003.

Year 2001

  1. R. R. Doering and Y. Nishi, "Limits of Integrated-Circuit Manufacturing," Special Issue on Limits of Semiconductor Technology, Proc. of the IEEE, Vol. 89, pp. 375-393, March 2001.

Year 1999

  1. 1. Y. Nishi and J. W. McPherson, "Impact of New Materials, Changes in Physics and Continued ULSI Scaling on Failure Mechanisms and Analysis," (invited) Proc. of 7th Int’l Symposium on Physical and Failure Analysis of Integrated Circuits, pp. 1-8, July 1999.

 

Year 1998

  1. Y. Nishi, " Surface States and Device Performance," (invited) Proc. 8th International Symposium on Silicon Materials Science and Technology, vol. 1, pp301-318, May 1998.

 

Pre 1998

  1. Y. Nishi, "Silicon-Based IC Technology for Giga-Scale Integration Era" (plenary invited), Proc. International Conference on Solid State Devices and Materials, pp. 4-5, September 1997.
  2. J. P. Snyder, Y. Nishi and C. R. Helms, "Experimental Investigation of a PtSi Source and Drain Field Emission Transistor," Appl. Physics Letters, vol. 67, pp. 1420-1422, 1995.
  3. T. A. Schreyer, Y. Nishi and K. C. Saraswat, "Simulation and Measurement of Picosecond Step Responses in VLSI Interconnections," IEDM Technical Digest , pp. 344-347, 1988.
  4. Y. Nishi, K. Taniguchi and J. Matsunaga, "Technology and Modeling for MOS IC/VLSIs," (invited), Physica, vol. 129 B, Solid State Devices, pp. 16-32, September 1984.
  5. Y. Nishi, "Silicon on Sapphire Technology," (invited), European Solid State Circuits Conference 1976, pp. 89-116, September 1976.
  6. Y. Nishi, K. Tanaka and A. Ohwada, "Study of Silicon-Silicon Dioxide Structure by Electron Spin Resonance II," Japan. J. Appl. Phys., vol. 11, pp. 85-91, January 1972.
  7. Y. Nishi, "Study of Silicon-Silicon Dioxide Structure by Electron Spin Resonance I," Japan. J. Appl. Phys., vol. 10, pp. 52-62, January 1971.

 
   
LAST UPDATE: 07/27/2008 CONTACT WEBMASTER
CENTER FOR INTEGRATED SYSTEMS, 420 VIA PALOU MALL, STANFORD UNIVERSITY, STANFORD, CA-94305